repo_name stringlengths 6 79 | path stringlengths 6 236 | copies int64 1 472 | size int64 137 1.04M | content stringlengths 137 1.04M | license stringclasses 15
values | hash stringlengths 32 32 | alpha_frac float64 0.25 0.96 | ratio float64 1.51 17.5 | autogenerated bool 1
class | config_or_test bool 2
classes | has_no_keywords bool 1
class | has_few_assignments bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_viv_comp.vhd | 12 | 8,921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 2a484c624e5188de7c4b05fe76ae2f52 | 0.923103 | 1.916022 | false | false | false | false |
rbarzic/arty-cm0-designstart | ips/clock_manager/arty_mmcm/arty_mmcm_sim_netlist.vhdl | 1 | 7,847 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.3 (lin64) Build 1368829 Mon Sep 28 20:06:39 MDT 2015
-- Date : Mon Nov 16 15:47:10 2015
-- Host : roba-OptiPlex-7010 running 64-bit Ub... | gpl-2.0 | d8f59d2146f68ab06b474173949c75e6 | 0.646617 | 3.37796 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_addsub_v12_0/hdl/c_addsub_v12_0_fabric_legacy.vhd | 3 | 16,399 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 00ed97a052dab6b9e4bb37fa9cb07db9 | 0.937374 | 1.872887 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/syn/vhdl/contact_discovery.vhd | 3 | 60,167 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | gpl-3.0 | 964cc43fc0de4748ccd894b6e658d5de | 0.604883 | 2.81628 | false | false | false | false |
amerryfellow/dlx | rocache/rocache.vhd | 1 | 6,369 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use work.ROCACHE_PKG.all;
entity ROCACHE is
port (
CLK : in std_logic;
RST : in std_logic; -- active high
ENABLE : in std_logic;
ADDRESS : in std_logic_vector(INSTR_SIZE - 1 downto 0);
OUT_DATA : out std_logic_vector(... | gpl-3.0 | ab20f8a91e9290ad0769e7031aabe54a | 0.610614 | 2.984536 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_exp/floating_point_v7_0_exp_table_pkg.vhd | 3 | 561,677 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 93c35fc3781665c312c9c043cc78cac8 | 0.955579 | 1.805455 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_log/flt_log_specialcase.vhd | 3 | 13,695 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | bc28c6d6b9c37019c10b16c28b90c1d3 | 0.932238 | 1.863519 | false | false | false | false |
UVVM/uvvm_vvc_framework | uvvm_util/src/bfm_common_pkg.vhd | 2 | 30,615 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit | e84e2cd423a50fec5185cf3bcf379f6d | 0.611857 | 3.758286 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/ipcore_dir/Instr_Mem.vhd | 13 | 5,601 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... | gpl-3.0 | f18c3064028ad7bc67cf3e2668139026 | 0.531334 | 3.94159 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | Lab4/VGADebug/VGADebug/keycode_to_ascii.vhd | 2 | 7,145 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
--... | gpl-3.0 | d9331915af0214bde67680fe94ce50e4 | 0.516025 | 2.424499 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Combined/TopLevel_tb.vhd | 1 | 3,627 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:28:39 03/31/2016
-- Design Name:
-- Module Name: /home/robert/UMD_RISC-16G5/ProjectLab1/Poject_Lab01/ProjLab1/TopLevel_tb.vhd
-- Project Name: ProjLab1
-- Target Device:
-- Tool ver... | gpl-3.0 | 2f34118a288e773ca047cadf1dc2965b | 0.574304 | 3.352126 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0_viv.vhd | 12 | 14,128 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 2f4c6202e10df3db245ad81a94873ef1 | 0.933182 | 1.862378 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_log/flt_log_lead_zero_encode.vhd | 3 | 23,317 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | eac18c7be6dc7c4baa5e2d26c758454f | 0.943175 | 1.847769 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/multi_fft/mult_gen_v12_0/hdl/ccm_dist_mem.vhd | 12 | 11,405 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 9926f29dfa45a5d073a2ebdf61ca92f0 | 0.928014 | 1.897986 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ALU/ALU/alu_toplevel.vhd | 1 | 2,789 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... | gpl-3.0 | 05f66c84753df7ae23528524b1eca0d5 | 0.57189 | 3.187429 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/DATAMEM/simulation/DATAMEM_tb.vhd | 1 | 4,316 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | gpl-3.0 | 61241ebc77b26a7033744701d2da4100 | 0.620019 | 4.645856 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/dsp48e1_wrapper.vhd | 3 | 34,794 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 8723314a54826e02475f78482821675f | 0.948123 | 1.834449 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_mult/fix_mult/fix_mult_xx.vhd | 2 | 16,658 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 407c99b4e9bd1d7197606c2a5d979034 | 0.938588 | 1.855424 | false | false | false | false |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_15kHz_0/synth/fir_lp_15kHz.vhd | 1 | 12,231 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-2.0 | ee9a42fc96b62a81af677975275f6157 | 0.654076 | 3.080856 | false | true | false | false |
UVVM/UVVM_All | uvvm_util/src/generic_queue_pkg.vhd | 1 | 50,840 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... | mit | dfc59561abbbb0dfacfa0d1165b6ef21 | 0.620791 | 4.198183 | false | false | false | false |
notti/dis_se | testbench/tb_shift.vhd | 1 | 1,640 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_shift is
end tb_shift;
architecture behav of tb_shift is
signal a : t_data := (others => '0');
signal b... | bsd-2-clause | 75e2cb150f9359d2c0cbc6c51d541c96 | 0.488415 | 3.534483 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_spi/src/vvc_cmd_pkg.vhd | 1 | 7,612 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... | mit | fc49140ea28b7284a058e55992354860 | 0.436416 | 5.188821 | false | false | false | false |
amerryfellow/dlx | basics/mux4to1.vhd | 1 | 899 | library IEEE;
use IEEE.std_logic_1164.all;
use WORK.alu_types.all;
--
-- Generic n-bit mux with two input vectors and one output vector
--
entity MUX4TO1 is
generic (
N: integer := NSUMG -- Number of bits
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
C: in... | gpl-3.0 | 6357b352580cff5b78528c7ab27cfd21 | 0.618465 | 2.483425 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/dither_wrap.vhd | 4 | 23,856 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | d98f923a6dfab43be41b192c95a6b81d | 0.941859 | 1.84202 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/r22_twos_comp_mux.vhd | 2 | 10,108 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | c5ae2639b4ed59087900bf617b712ce3 | 0.923823 | 1.902503 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_mult/flt_mult_round/flt_round_dsp_opt_full.vhd | 3 | 23,446 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 2a1930a5b85aecdf3e65192d765d81c6 | 0.941653 | 1.841357 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/mux_bus2.vhd | 3 | 10,757 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 0da5eec17df61a164da2fdd5867a4309 | 0.926095 | 1.893838 | false | false | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_spi/src/vvc_cmd_pkg.vhd | 2 | 8,079 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit | 79335de8065077cba07f76f8bc215aad | 0.449065 | 5.087531 | false | false | false | false |
amerryfellow/dlx | dlx.vhd | 1 | 18,005 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use work.CONSTANTS.all;
use work.ROCACHE_PKG.all;
use work.RWCACHE_PKG.all;
use work.alu_types.all;
use work.cu.all;
entity DLX is
port (
-- Inputs
CLK : in std_logic; -- Cl... | gpl-3.0 | 3126e1441cd0ee342edaaede6b96b731 | 0.653207 | 2.585068 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/Instr_Mem1/simulation/Instr_Mem1_synth.vhd | 2 | 7,895 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | gpl-3.0 | be57b0eaaaba40be54e7517f0a873ee5 | 0.565548 | 3.766698 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_recip/flt_recip_postprocess.vhd | 3 | 18,648 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | de48ccbe5e61ccd4cac4f7cedaf2e355 | 0.938975 | 1.854047 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi/solution1/syn/vhdl/contact_discovery_AXILiteS_s_axi.vhd | 3 | 34,912 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IE... | gpl-3.0 | 7367bcda35966e544a7c0403d7935422 | 0.501289 | 3.462462 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/twgen_quarter_sin.vhd | 2 | 23,317 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 39400545216f1a61195661fb495fbcab | 0.941931 | 1.84295 | false | false | false | false |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_rst_processing_system7_0_100M_0/sim/system_rst_processing_system7_0_100M_0.vhd | 1 | 6,061 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does no... | mit | 2480190c1d7df06f7799489060e3bb26 | 0.693285 | 3.573703 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_addsub_v12_0/hdl/c_addsub_v12_0_viv_comp.vhd | 3 | 9,654 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 8ad7d9dd9ef3d803f8adee790f8758ed | 0.922623 | 1.895915 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/accum.vhd | 4 | 48,970 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 08af706d5a38e2d183c13583a6030222 | 0.948703 | 1.829697 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fir/fir_compiler_v7_1/hdl/mem.vhd | 2 | 16,549 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 77a5ca04908b6894643e4e5927af58fe | 0.939453 | 1.859856 | false | false | false | false |
fafaldo/ethernet | ethernet4b/vga_display.vhd | 1 | 3,955 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_display is
Port ( char : out STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
char_we : out STD_LOGIC := '0';
clk : in STD_LOGIC;
ram_enable : out STD_LOGIC := '1';
ram_output : in STD_LOGIC_VECTOR(7 dow... | apache-2.0 | 8db30783550411b53ab63d1e5fb4b167 | 0.500379 | 2.960329 | false | false | false | false |
freecores/light8080 | vhdl/demo/rs232_tx.vhdl | 1 | 1,597 | --##############################################################################
-- RS-232 transmitter, hardwired to 9600 bauds when clocked at 50MHz.
-- WARNING: Hacked up for light8080 demo. Poor performance, no formal testing!
-- I don't advise using this for any purpose.
--##########################################... | gpl-3.0 | 2c7bbfd5cc21e87717fe0fa5bca2fab7 | 0.50407 | 3.464208 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_exp/flt_exp_e2A.vhd | 3 | 13,006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | d7819aa9f253195b4f32bce6e2509349 | 0.931339 | 1.881111 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/ipcore_dir/Instr_Mem/example_design/Instr_Mem_prod.vhd | 1 | 10,083 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confide... | gpl-3.0 | f79dc08436e0344f4504582b168b623b | 0.493008 | 3.826565 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_div/flt_div_mant.vhd | 2 | 29,821 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | eb3fff3c0acb55065190e79bda629449 | 0.946212 | 1.838079 | false | false | false | false |
UVVM/uvvm_vvc_framework | uvvm_util/src/string_methods_pkg.vhd | 1 | 50,359 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit | bec19f0c406465d019cd6f55010bdbe3 | 0.581723 | 3.781841 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_spi/src/spi_bfm_pkg.vhd | 1 | 72,549 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... | mit | 17124b77e8b1ed15a9fe2b8ce11fb348 | 0.510055 | 4.034086 | false | true | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_spi/src/vvc_methods_pkg.vhd | 1 | 61,035 | --========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit | 6522542183cbc6e4e7ae3753875c4671 | 0.544212 | 4.129846 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_add/flt_add_logic.vhd | 2 | 31,681 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | d5a35e20d4936eb8a2b015e3c1e6c0e7 | 0.946782 | 1.836154 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/r2_rw_addr.vhd | 2 | 16,658 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 52a8c33a729c42cca7c92a04efbf039d | 0.937748 | 1.845762 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/floating_point_v7_0_viv.vhd | 3 | 132,705 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 9daa0f863e52827207acd2aa09532ff9 | 0.953227 | 1.815564 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_shift_ram_v12_0/hdl/prim_wrappers_v12_0_legacy.vhd | 3 | 11,470 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 6b5294e39816e99c191769f9026b0d9e | 0.927724 | 1.886203 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/NewCombined/ipcore_dir/Instr_Mem.vhd | 1 | 5,602 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... | gpl-3.0 | 39a12aeb3059c7972e2997b3f17058e3 | 0.531417 | 3.942294 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/HardwareDebugDemo/SevenSeg.vhd | 8 | 4,031 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: SevenSeg
-- Project Name: SevenSegmentDisplay
-- Target Devices: Spartan-3E
-- T... | gpl-3.0 | 037676c3b2fd88616d06a33eda81cc18 | 0.465641 | 3.850048 | false | false | false | false |
skordal/potato | src/pp_execute.vhd | 1 | 14,208 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_csr.all;... | bsd-3-clause | 6435d416f525c82bb476ade994c96a1e | 0.654139 | 2.865672 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/dds/dds_compiler_v6_0/hdl/dds_compiler_v6_0_rdy.vhd | 6 | 11,385 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 5a4e1654996e39918301ae524a854ed0 | 0.929117 | 1.893713 | false | false | false | false |
notti/dis_se | testbench/tb_mp.vhd | 1 | 48,062 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_mp is
end tb_mp;
architecture behav of tb_mp is
signal rst : std_logic := '1';
signal clk ... | bsd-2-clause | 36ac8dc1fb0240cb3fca6b7e0fcadaa3 | 0.297699 | 3.01897 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_input_block.vhd | 11 | 45,404 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 42df289afcc7fded1564a6972cad54c2 | 0.949234 | 1.825286 | false | false | false | false |
amerryfellow/dlx | alu/multiplier/booth.vhd | 1 | 2,832 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use WORK.alu_types.all;
-- This entity implements a signed multiplication.
entity BOOTHMUL is
generic (
N : integer := NSUMG
);
port (
A : in std_logic_vector(N-1 downto 0);
B : in std_logic_... | gpl-3.0 | c273e6cae2bf4cbaec8ee18a1b9f9c04 | 0.638065 | 2.892748 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_bram18k_v3_0/hdl/xbip_bram18k_rtl.vhd | 12 | 22,883 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 38f667a208b8113c6761587f0d6e9a34 | 0.940392 | 1.840653 | false | false | false | false |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_i2s_adi/axi_i2s_adi.vhd | 1 | 12,751 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.i2s_controller;
library work;
use work.axi_streaming_dma_rx_fifo;
use work.axi_streaming_dma_tx_fifo;
use work.pl330_dma_fifo;
use work.axi_ctrlif;
entity ax... | gpl-3.0 | effd10e8ee02ed3e756c4e0e2c846596 | 0.608109 | 2.508065 | false | false | false | false |
fafaldo/ethernet | ethernet4b/IPv4_destination.vhd | 1 | 1,408 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.... | apache-2.0 | 829e05829face77c9e282c096774f1cc | 0.692472 | 3.312941 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_experimental/solution1/syn/vhdl/contact_discovery.vhd | 3 | 282,362 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.s... | gpl-3.0 | 48ff57db7931d3b6331f88459a6dd06d | 0.671698 | 2.827041 | false | false | false | false |
notti/dis_se | vhdl/soc.vhd | 1 | 2,368 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity soc is
port(
rst : in std_logic;
clk : in std_logic;
clk2x : in std_logic;
pc : out std_logic_vector(7 downto 0);
rx : ... | bsd-2-clause | 18cad62d3735265ef84f6b0fc7a4e210 | 0.558699 | 3.111695 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/mux_bus4.vhd | 3 | 20,743 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 27fdcd90863bee392f3e2d8af0c5cc1c | 0.941812 | 1.864707 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd | 11 | 57,813 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 1fc3754de7635d7b9821c39b9e70a33b | 0.951066 | 1.8218 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | JumpUnit/ECE368_Project_Lab1_Team5/alu_toplevel.vhd | 1 | 3,855 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:02 03/28/2016
-- Design Name:
-- Module Name: ALU_Toplevel - Dataflow
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revi... | gpl-3.0 | f8bee4fea3098bfd08b03cbe5c05cf96 | 0.548379 | 2.916036 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/pipe_add.vhd | 4 | 8,921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 9fc67bbd76ee6320c7620c3109e97e26 | 0.919404 | 1.907419 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/sim/fft.vhd | 2 | 10,198 | -- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... | gpl-2.0 | c5bd118f4ea6e1e0237d09222339f8d6 | 0.680918 | 3.327243 | false | true | false | false |
UVVM/uvvm_vvc_framework | bitvis_vip_axistream/src/vvc_context.vhd | 1 | 1,470 | --========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@... | mit | 316b8c9773fbff9642eb398d3b4a80b2 | 0.542177 | 5.444444 | false | false | false | false |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_axi_one_db_load/solution1/syn/vhdl/contact_discoverycud.vhd | 3 | 4,164 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
--
library ieee;
us... | gpl-3.0 | 4a6a7c8b6ae35b5a79c384e4f28ba05a | 0.548031 | 3.525826 | false | false | false | false |
amerryfellow/dlx | packages/cuTypes.vhd | 1 | 2,879 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cu is
-- Control unit input sizes
constant OPCODE_SIZE : integer := 6; -- OPCODE field size
constant FUNC_SIZE : integer := 11; -- FUNC field size
subtype OPCODE_TYPE is std_logic_vector(OPCODE_SIZE - 1 downto 0);
-- I-Type instructi... | gpl-3.0 | 8685f34ad9ea2df4df5158c2d5131b7e | 0.678361 | 2.797862 | false | false | false | false |
UVVM/UVVM_All | uvvm_util/src/uvvm_util_context.vhd | 1 | 1,885 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... | mit | 0f9f7bd9d7f4f9efb769bcbc5b47cd10 | 0.529443 | 5.108401 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/dds_compiler_v6_0_viv_comp.vhd | 4 | 19,297 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 1aa0f575660299d7990adc5edae8b136 | 0.940664 | 1.865706 | false | false | false | false |
keith-epidev/VHDL-lib | top/mono_radio/ip/clk_108MHz/clk_108MHz_funcsim.vhdl | 2 | 7,474 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 1 20:55:21 2014
-- Host : macbook running 64-bit Arch Linux
-- ... | gpl-2.0 | 90f82bd540c40d638175630687db0e33 | 0.618009 | 3.315883 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r22_bf.vhd | 3 | 42,356 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 88be1560f67b9a7e1ee1bfc8ac52efd9 | 0.949145 | 1.830977 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/sub_byp.vhd | 2 | 9,156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | cab2afed935dd9a2a9f32f129ae8b033 | 0.922892 | 1.911482 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fir/axi_utils_v2_0/hdl/axi_utils_v2_0_pkg.vhd | 10 | 8,183 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 47fcaed28659559b5febfc63a4da82e8 | 0.918734 | 1.924959 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/ipcore_dir/DEBUG_RAM/simulation/DEBUG_RAM_synth.vhd | 2 | 8,888 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... | gpl-3.0 | 96d57245460a1c5265ffa01b5915a764 | 0.568407 | 3.589661 | false | false | false | false |
fafaldo/ethernet | ethernet4b/netgen/par/nowyRXTX_timesim.vhd | 1 | 284,467 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.68... | apache-2.0 | 37e00ce2de6aa0417bd1de7af103b93f | 0.54509 | 2.999663 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/pkg_dds_compiler_v6_0.vhd | 4 | 179,717 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 74205ffbf274332f472bb1b05df23e4f | 0.954434 | 1.808764 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48e1_wrapper_v3_0.vhd | 7 | 25,627 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 18163f7b2f3e9a89e82ccc4b948b1480 | 0.944082 | 1.843536 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/logical_unit.vhd | 8 | 1,684 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:37:34 03/28/2016
-- Design Name:
-- Module Name: logical_unit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Re... | gpl-3.0 | ace1b6c8be48647e74671aa19cbaa169 | 0.577791 | 3.45082 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/cmpy_v6_0/hdl/cmpy_3_dsp48_mult.vhd | 3 | 21,218 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 1be6c0eb7482f825e6ef72e8d4d1aa93 | 0.939014 | 1.836261 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fir/fir_compiler_v7_1/hdl/add_sub.vhd | 2 | 15,965 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | e963deec65508b965ebd6723a0967400 | 0.937739 | 1.862894 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_addsub_v3_0/hdl/xbip_addsub_v3_0_viv_comp.vhd | 3 | 7,989 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | e0fec39c91aa597d2b303e779dc03381 | 0.915384 | 1.940962 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/mult_gen_v12_0/hdl/dsp.vhd | 12 | 181,273 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 2dd6ee33e7aff5f5f2fa8ccfa36025e7 | 0.954196 | 1.813111 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/bfly_byp.vhd | 2 | 9,934 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | ec314cf4cc704273844850487b56293f | 0.923696 | 1.910752 | false | false | false | false |
tdene/synth_opt_adders | src/pptrees/mappings/behavioral_map.vhd | 1 | 7,904 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity and2 is
port (
A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end entity;
architecture behavior of and2 is
begin
Y <= A and B;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;... | apache-2.0 | 3235089101576ed24c22e410f1acaa6c | 0.646635 | 2.855491 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_mux_bit_v12_0/hdl/c_mux_bit_32to1.vhd | 3 | 26,081 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | fa63f222fa27c34ee9d52d375ff49522 | 0.943675 | 1.840709 | false | false | false | false |
UVVM/UVVM_All | bitvis_vip_avalon_st/src/vvc_methods_pkg.vhd | 1 | 25,282 | --================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the ... | mit | e8a88584ce9a8ace6957201733991e24 | 0.536825 | 4.261969 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | Lab4/VGADebug/VGADebug/pixel_clk.vhd | 5 | 1,030 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx... | gpl-3.0 | ab56da878b2c08d542ade68ffd6c9a80 | 0.590291 | 3.718412 | false | false | false | false |
skordal/potato | testbenches/tb_soc_uart.vhd | 1 | 2,768 | -- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
entity tb_soc_uart is
end entity tb_soc_uart;
architecture testbench... | bsd-3-clause | 48d801d3d4f240a5183604a053cb7eae | 0.593569 | 2.5845 | false | false | false | false |
keith-epidev/VHDL-lib | top/mono_radio/ip/multi_QI/multi_QI_funcsim.vhdl | 1 | 785,092 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 12 11:42:56 2014
-- Host : macbook running 64-bit Arch Linux
-- ... | gpl-2.0 | be61be57032aaebbe5d50a0c10aa1350 | 0.952417 | 1.815158 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/c_shift_ram_v12_0/hdl/c_shift_ram_v12_0_viv.vhd | 3 | 12,268 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | a1f2060630beb1c57812477c3ca2e8b0 | 0.92998 | 1.885644 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_log/flt_log_L_block.vhd | 2 | 25,108 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 98815b9324397b4469ef6df5e06daf02 | 0.9444 | 1.846584 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Register/Lab04/vga_driver.vhd | 10 | 3,053 | ---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Toplevel
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versi... | gpl-3.0 | c736c3497df73990cf24904a1649420f | 0.511628 | 3.617299 | false | false | false | false |
notti/dis_se | vhdl/top.vhd | 1 | 1,520 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity top is
port(
rst : in std_logic;
clk : in std_logic;
pc : out std_logic_vector(7 downto 0);
rx : in std_logic;
tx : ... | bsd-2-clause | 397b987f5eb1ad50decf83c50253e714 | 0.484211 | 3.340659 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_fma/flt_fma_mul.vhd | 2 | 12,896 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 6f0eab306313ea1eec994da8179b3cc5 | 0.929746 | 1.884554 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_log/flt_log_taylor.vhd | 3 | 41,558 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 91764c70831c1d2b17c2c87cda4126d7 | 0.946701 | 1.832848 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/EXTERNAL_MEMORY.vhd | 4 | 5,683 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx ... | gpl-3.0 | bc9d09c68b99562d74d0f7b6608c28b0 | 0.53792 | 3.993675 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/butterfly_dsp48e_bypass_hybrid.vhd | 3 | 37,582 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | 555355cee3e57436f13d373e67ead206 | 0.948805 | 1.836045 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_recip/flt_recip_reduction_calc.vhd | 3 | 12,702 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... | gpl-2.0 | a75bbbcda63540bf363d2f6f62d7d1f7 | 0.933632 | 1.889897 | false | false | false | false |
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