Split (1)

train · 36.5k rows

repo_name stringlengths 6 79	path stringlengths 6 236	copies int64 1 472	size int64 137 1.04M	content stringlengths 137 1.04M	license stringclasses 15 values	hash stringlengths 32 32	alpha_frac float64 0.25 0.96	ratio float64 1.51 17.5	autogenerated bool 1 class	config_or_test bool 2 classes	has_no_keywords bool 1 class	has_few_assignments bool 1 class
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/c_mux_bit_v12_0/hdl/c_mux_bit_v12_0.vhd	3	11,470	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	f58696b36a009bd4d5dcd7e9ce6e2ce2	0.929904	1.890244	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/pkg_beta.vhd	4	604,473	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	4869f63210174a4598d446c449b7aaf7	0.955846	1.807116	false	false	false	false
amerryfellow/dlx	alu/shifter/barrelshifter.vhd	1	4,864	library IEEE; use IEEE.std_logic_1164.all; use WORK.alu_types.all; Entity bshift is -- barrel shifter generic(N:integer:=NSUMG); port ( direction : in std_logic; -- '1' for left, '0' for right logical : in std_logic; -- '1' for logical, '0' for arithmetic shift : in st...	gpl-3.0	ff1c1542d5923ef01091f0fb72159cf8	0.605263	2.433217	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/r2_ovflo_gen.vhd	2	8,682	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	75d079151856cdcb2e3f2a8def61fee4	0.919373	1.937514	false	false	false	false
skordal/potato	src/pp_alu_mux.vhd	1	1,392	-- The Potato Processor - A simple processor for FPGAs -- (c) Kristian Klomsten Skordal 2014 <kristian.skordal@wafflemail.net> -- Report bugs and issues on <https://github.com/skordal/potato/issues> library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_types.all; --! @brief Multiplexer use...	bsd-3-clause	093673d02b6d3c46fbb12385311d8c04	0.674569	3.059341	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/dds/demo_tb/tb_dds.vhd	3	8,717	-------------------------------------------------------------------------------- -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property ...	gpl-2.0	0f1459c2994f09a37679c7f692e7417f	0.561317	4.840089	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/VHDL-Template-TestBench.vhd	1	2,618	--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Class: ECE 368 Digital Design -- Engineer: [Engineer 1] -- [Engineer 2] -- -- Create Date: [Date] -- Module Name: [Module Name] -- Proj...	gpl-3.0	80b8a5b95d2a3fad27c481af5ea09b37	0.536287	3.514094	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/VGA_Debug_Unit/ipcore_dir/DEBUG_RAM.vhd	1	5,786	-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx ...	gpl-3.0	e0651428556fc80d90a1f41a51d2443d	0.533356	3.9174	false	false	false	false
amerryfellow/dlx	rwcache/testbench.vhd	1	3,545	library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use std.textio.all; use work.RWCACHE_PKG.all; entity TBCACHE is end TBCACHE; architecture TB_1 of TBCACHE is component RWCACHE is port ( CLK : in std_logic; RST : in std_logic; -- active high ENABLE : in std_logic; READN...	gpl-3.0	d8676348efbd2d5a395040119dc96d5d	0.627362	2.767369	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab2/Shadow_Register/Lab04/programCounter.vhd	7	1,104	-- Company: Team 5 -- Engineer: -- -- Create Date: 15:15:57 03/11/2016 -- Design Name: -- Module Name: programCounter - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ----...	gpl-3.0	cdcb4b2b883e679615afcd8e46bbdce7	0.595109	3.266272	false	false	false	false
notti/dis_se	vhdl/mp_stage2.vhd	1	2,272	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity mp_stage2 is port( rst : in std_logic; clk : in std_logic; cmd_in : in t_vliw; arg_in : in t_data_array(5 downto 0); val_in : i...	bsd-2-clause	5a2dd20173eb4fe2f5d0cbde1f57a7fe	0.547095	2.666667	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/VGA_Debug_Unit/ipcore_dir/DEBUG_RAM/simulation/DEBUG_RAM_synth.vhd	1	8,891	-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains c...	gpl-3.0	91fc88f4b4f2e02b0339ff497ece24d4	0.568552	3.590872	false	false	false	false
keith-epidev/VHDL-lib	src/components/vga/vga.vhd	1	1,673	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity vga is generic( Hsync:integer := 208; Hact:integer := 1920; Hfp:integer := 128; Hbp:integer := 336; Vsync:integer := 3; Vact:integer :=...	gpl-2.0	659312709d823b87c5f26bacb228a249	0.591751	2.618153	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/zero_det_sel.vhd	2	28,115	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	3ae178392df847600c0bda89bdf19a56	0.944727	1.843607	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/clk_108MHz/clk_108MHz_clk_wiz.vhd	2	7,397	-- file: clk_108MHz_clk_wiz.vhd -- -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaime...	gpl-2.0	a141a38cb5fcd6573150adf2345cbd6a	0.573611	4.234116	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/xfft_v9_0/hdl/cnt_sat.vhd	3	12,248	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	80016fec973f6cca1d28cbbfb6688212	0.931091	1.893045	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/fir_compiler_v7_1.vhd	8	19,272	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	1fc5bc491db4a41fe5d87b66b19303b8	0.938719	1.845977	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_log/flt_log_lead_zero_encode.vhd	2	23,317	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	7c57e371bd74604e28ffa72d7a4d119d	0.942274	1.854087	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/c_addsub_v12_0/hdl/c_addsub_v12_0_legacy.vhd	2	57,574	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	fd4cc6184ea60e6e346b652dd2e23441	0.951871	1.819716	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/dds/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_comp.vhd	6	8,876	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	22062fa89800cb044701a2cc014b0c2a	0.919671	1.914995	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab2/Shadow_Register/Lab04/Lab04/ipcore_dir/DEBUG_RAM/example_design/DEBUG_RAM_exdes.vhd	5	5,155	-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7.1 Core - Top-level core wrapper -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. -- -- This fi...	gpl-3.0	9a260255194ba7f131a74484d4138e89	0.538312	4.482609	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd	3	8,572	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	08392edcdb51add56f434db6cc0f2673	0.921022	1.939805	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_fma/flt_fma_addsub.vhd	3	16,873	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	c12442b62c570ecbb234b46710df93d9	0.937415	1.865038	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/c_mux_bit_v12_0/hdl/c_mux_bit_32to1.vhd	2	26,081	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	cc8825418633b2339d73f7faeb4bcd07	0.944864	1.841618	false	false	false	false
skordal/potato	src/pp_types.vhd	1	3,552	-- The Potato Processor - A simple processor for FPGAs -- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net> -- Report bugs and issues on <https://github.com/skordal/potato/issues> library ieee; use ieee.std_logic_1164.all; package pp_types is --! Type used for register addresses. subtype ...	bsd-3-clause	a963cd6acc7684c03d75e4d440bb1fa9	0.692005	3.07799	false	true	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/VGA_Debug_Unit/alu_arithmetic_unit.vhd	1	1,654	--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2015 -- Module Name: ALU_Arithmetic_Unit -- Project Name: ALU -- Target Devices: Spartan-3E -- Too...	gpl-3.0	1583f1b46aa3cf9eaddb8774c999e992	0.53688	3.511677	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/vt2m/vt2mArch.vhd	2	137,090	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	586bedefadb1b1b6ef5282742ade7142	0.953979	1.812904	false	false	false	false
keith-epidev/VHDL-lib	top/mono_radio/ip/fir_lp_15kHz/demo_tb/tb_fir_lp_15kHz.vhd	1	10,090	-------------------------------------------------------------------------------- -- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property ...	gpl-2.0	6e803082f4760dd8957b874a1a856619	0.57116	4.788799	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fir/fir_compiler_v7_1/hdl/polyphase_decimation.vhd	2	380,184	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	db09968205a63b26d58b280782b53775	0.955424	1.809039	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/xfft_v9_0/hdl/out_switch4.vhd	3	13,739	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	fda327a91a2fa60e77d821261b54fee8	0.932746	1.867219	false	false	false	false
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA	System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/ip/HLS_accel_ap_faddfsub_3_full_dsp_32.vhd	2	13,345	-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does no...	mit	87e4a36bc54f9e77757e899713ac93da	0.640989	3.058675	false	false	false	false
notti/dis_se	testbench/tb_serial.vhd	1	1,460	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_serial is end tb_serial; architecture behav of tb_serial is signal rst : std_logic := '1'; signal clk :...	bsd-2-clause	09a647143b2741a7eafe2f5e020f42d7	0.478767	3.552311	false	false	false	false
amerryfellow/dlx	cu/cu.vhd	1	10,327	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use work.alu_types.all; use work.cu.all; --use work.all; entity CU_UP is generic ( MICROCODE_MEM_SIZE : integer := 57; -- U Microcode Memory Size -- OPCODE_SIZE : integer := 6; -- Op Code Size -- FUNC_SIZE : ...	gpl-3.0	03eea085c1c748aaba9b9535ceb2af51	0.571027	2.573386	false	false	false	false
keith-epidev/VHDL-lib	top/lab_2/part_3/ip/bram/bram/bram_funcsim.vhdl	1	28,035	-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013 -- Date : Wed Mar 19 14:18:40 2014 -- Host : macbook running 64-bit Arc...	gpl-2.0	91ee1841eed573c48e6e9c6f673f324f	0.709328	4.327057	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/dds/dds_compiler_v6_0/hdl/dds_compiler_v6_0_core.vhd	6	81,480	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	93587938ad83d7c5990acbf9b678e37c	0.952123	1.819237	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/Poject_Lab01/Project1/RegisterBank.vhd	1	4,995	---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S5...	gpl-3.0	4689ec62fe4a03a4708add973e386ed8	0.512112	2.746014	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/xfft_v9_0/hdl/so_ranger.vhd	3	9,051	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	c28c7c0eee67ba8e8b067b79a8579cb8	0.920782	1.910703	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab2/NewCombined/ipcore_dir/instruction_memory/simulation/instruction_memory_synth.vhd	5	7,943	-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains c...	gpl-3.0	a82dcc186300520668d673174201584d	0.568173	3.800478	false	false	false	false
notti/dis_se	vhdl/cpu.vhd	1	19,291	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.procedures.all; entity cpu is port( rst : in std_logic; clk : in std_logic; clk2x : in std_logic; ena : out std_logic; addra : out t_data2; ...	bsd-2-clause	9c4176380fefe04109cd779f303e76f3	0.452335	3.469604	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/compare_ge.vhd	2	11,320	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	7d3fc034953d0d9ab54c6eccf35c8fd3	0.92818	1.884782	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_exp/flt_exp_e2zmzm1.vhd	3	14,258	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	073506372dcb210d6acf54556726eeca	0.932459	1.854096	false	false	false	false
skordal/potato	testbenches/tb_soc_gpio.vhd	1	2,126	-- The Potato Processor - A simple processor for FPGAs -- (c) Kristian Klomsten Skordal 2014 - 2016 <kristian.skordal@wafflemail.net> -- Report bugs and issues on <https://github.com/skordal/potato/issues> library ieee; use ieee.std_logic_1164.all; entity tb_soc_gpio is end entity tb_soc_gpio; architecture testbench...	bsd-3-clause	61e4cbdeed3efd9cf76019cb31961d00	0.607714	2.561446	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_fma/flt_fma_add_logic.vhd	2	25,931	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	8ef8a469659caac54a49618c0624e5d7	0.944391	1.83245	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_exp/floating_point_v7_0_exp_table_pkg.vhd	2	561,677	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	ba4f24f4b5509dc508cbf0cdd0c43914	0.955779	1.806959	false	false	false	false
r2t2sdr/r2t2	fpga/modules/te/SC0720/SC0720.vhd	1	2,430	---------------------------------------------------------------------------------- -- Company: Trenz Electronic GmbH -- Engineer: Antti Lukats -- -- Create Date: 13.11.2013 09:58:03 -- Design Name: -- Module Name: SC0720 - Behavioral -- Project Name: -- Target Devices: TE0720 SoM -- Tool Versions: 2014.4 -- Descrip...	gpl-3.0	b775757294da58530c401f85929ac492	0.559259	2.786697	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/mult_gen_v12_0/hdl/ccm_dist_mem.vhd	12	11,405	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	18ef8da90254ce2950a25bf952332f68	0.926786	1.878913	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/renorm_and_round_logic.vhd	2	50,680	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	96100991584645988dca427254c2b127	0.951638	1.834039	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/fir_lp_54kHz/fir_compiler_v7_1/hdl/add_sub.vhd	8	15,965	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	73aafd021b4b7dcf3ff0614f9b6c8167	0.938052	1.878456	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/dds/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0.vhd	6	9,610	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	bc3c876f4304a58a863cd15290c96a8b	0.921228	1.877687	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_recip/flt_recip_reduction_calc.vhd	2	12,702	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	f0ea20c45cbf59215b89dc442657c3b6	0.932294	1.886249	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_recip/flt_recipsqrt_dp_recsqrt_r_rom.vhd	3	28,674	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	7975a6067e01b0122df0eb67bf7d8972	0.946921	1.841737	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_3/ip/clk_base/clk_base_funcsim.vhdl	1	7,927	-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 -- Date : Tue May 13 23:58:38 2014 -- Host : macbook running 64-bit Arch Linux -- ...	gpl-2.0	b1a72d3e74a72a5dc832d057d189b011	0.625962	3.297421	false	false	false	false
notti/dis_se	testbench/tb_mp_indirect_fetch.vhd	1	3,894	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_mp_indirect_fetch is end tb_mp_indirect_fetch; architecture behav of tb_mp_indirect_fetch is signal rst ...	bsd-2-clause	5d5ca39af13433c505a85dbe85a6dc73	0.446584	3.120192	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/cmpy_v6_0/hdl/cmpy_3_mult18_lut.vhd	3	47,633	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	b0ddc12f2d75168edeb074733b3a7497	0.949741	1.82761	false	false	false	false
keith-epidev/VHDL-lib	src/VHDL_lib.vhd	1	8,866	library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned; use IEEE.NUMERIC_STD.ALL; package VHDL_lib is function next_power_2(len: positive) return positive; function char2int(arg : character) return natural; function test_factor(input:std_logic_vector; value: integer; factor: integer) retu...	gpl-2.0	2ddd4ecbdc96c0ee14048f42269dc3db	0.643244	2.86	false	false	false	false
UVVM/UVVM_All	bitvis_vip_axilite/src/vvc_methods_pkg.vhd	1	36,869	--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the ...	mit	5bd27fbe1efd1fabc4105b15661d4af7	0.571618	4.077978	false	true	false	false
r2t2sdr/r2t2	fpga/modules/adi_hdl/library/axi_i2s_adi/i2s_controller.vhd	1	8,890	-- ************************************************************************* -- ************************************************************************* -- Copyright 2013(c) Analog Devices, Inc. -- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com> -- -- All rights reserved. -- -- Redistribution and use...	gpl-3.0	8ce018d8b6146e46a6f01fdf7b562176	0.621597	2.982221	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab1/Poject_Lab01[old]/RegisterBank2 (3-25-16)/RegisterBank2/RegisterBank.vhd	3	3,889	---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS (cparks1@umassd.edu) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S5...	gpl-3.0	e0b1733f473e1c41199fb7fb04a76394	0.547699	2.908751	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/c_reg_fd_v12_0/hdl/c_reg_fd_v12_0.vhd	2	8,572	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	c696d0f6030ff06202a13fe5211bb053	0.919972	1.920681	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/mult_gen_v12_0/hdl/ccm_sp_block_mem.vhd	12	13,610	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	551ba920340f97baf37acfbb7f404b04	0.931007	1.866173	false	false	false	false
keith-epidev/VHDL-lib	top/lab_6/ip/dds/demo_tb/tb_dds.vhd	1	8,723	-------------------------------------------------------------------------------- -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property ...	gpl-2.0	45c84d157e2058977f7c6e0f37709f2e	0.561619	4.84342	false	false	false	false
UVVM/UVVM_All	bitvis_vip_sbi/src/transaction_pkg.vhd	1	5,988	--================================================================================================================================ -- Copyright 2020 Bitvis -- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- You may obtain a copy of the ...	mit	2388c7ef76df8680e43a6b0d3fc8d24e	0.494823	4.940594	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/addsub_dsp.vhd	3	30,579	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	0f16f0928f7c012a0352ff9087ecbf58	0.94614	1.836246	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_pkg.vhd	8	24,914	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	3c177a38549195ca13bba2fde329a20b	0.944529	1.858976	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/norm_zero_det.vhd	2	26,125	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	9c891d294d41d51588f6734450f67f04	0.944498	1.841475	false	false	false	false
keith-epidev/VHDL-lib	src/components/prn32/prn32.vhd	1	713	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.VHDL_lib.all; entity prn32 is generic( n: integer:= 4; seed: std_logic_vector:= X"12345678" ); port( clk: in std_logic; pn_val: out std_logic_vector(n-1 downto 0) ); end prn32; architecture break_out of prn32 is signal pn: std_logic...	gpl-2.0	27142e68e2eb93c911d916982822899c	0.653576	2.475694	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/shared/special_detect.vhd	2	15,251	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	6314ab0df6752b1f5eabdad8a9c7116c	0.936004	1.858292	false	false	false	false
mcoughli/root_of_trust	operational_os/hls/contact_discovery_hls_2017.1/solution1/syn/vhdl/contact_discoverybkb.vhd	3	3,125	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== -- library ieee; us...	gpl-3.0	9ec9a732d3254391142de9ff3d13b1d4	0.54912	3.621089	false	false	false	false
freecores/light8080	vhdl/test/light8080_tb0.vhdl	1	20,417	-------------------------------------------------------------------------------- -- Generated from template tb_template.vhdl by hexconv.pl -------------------------------------------------------------------------------- -- Light8080 simulation test bench. ----------------------------------------------------------------...	gpl-3.0	f66f16ea5a974513b2949305f0d3277d	0.529608	1.826208	false	false	false	false
keith-epidev/VHDL-lib	src/components/mux/mux.vhd	1	1,170	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.VHDL_lib.all; entity mux is generic( size:integer := 4 ); port ( s : in std_logic_vector(log2(size)-1 downto 0); input : in std_logic_vector(size-1 downto 0); output : out std_logic ); end mux; architecture arch of mux is si...	gpl-2.0	f837b4238f1d8e436325b070f92a0d6c	0.637607	2.702079	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/xfft_v9_0/hdl/tw_gen_p2.vhd	3	38,834	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	cfa71b35830c93842a8610c52b7e9888	0.946954	1.82585	false	false	false	false
UVVM/uvvm_vvc_framework	uvvm_vvc_framework/src/ti_data_fifo_pkg.vhd	2	8,926	--======================================================================================================================== -- Copyright (c) 2017 by Bitvis AS. All rights reserved. -- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not, -- contact Bitvis AS <support@...	mit	1fb255056189a2ac1e3b3cfd3351bf83	0.537867	4.392717	false	false	false	false
notti/dis_se	testbench/tb_mp_stage3.vhd	1	3,860	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library std; use std.textio.all; library work; use work.all; use work.procedures.all; entity tb_mp_stage3 is end tb_mp_stage3; architecture behav of tb_mp_stage3 is signal clk : std_logic := '0'; sig...	bsd-2-clause	05d9fc90e7ca9a5a899c2e61d58769c9	0.49171	3.065925	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/xbip_utils_v3_0/hdl/xbip_utils_v3_0_pkg.vhd	20	141,590	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	b81586b552b5cfb2b21582553b502e28	0.953839	1.813675	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/rw_addr_gen_b.vhd	2	64,362	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	ac1759327864d41c998afe9c9c08461a	0.951322	1.822718	false	false	false	false
skordal/potato	src/pp_core.vhd	1	15,290	-- The Potato Processor - A simple processor for FPGAs -- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net> -- Report bugs and issues on <https://github.com/skordal/potato/issues> library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.pp_types.all; use work.pp_constant...	bsd-3-clause	900131e160e1d819f493cdae6075fde9	0.646109	2.923518	false	false	false	false
UVVM/uvvm_vvc_framework	xConstrRandFuncCov/src/AlertLogPkg.vhd	2	159,459	-- -- File Name: AlertLogPkg.vhd -- Design Unit Name: AlertLogPkg -- Revision: STANDARD VERSION -- -- Maintainer: Jim Lewis email: jim@synthworks.com -- Contributor(s): -- Jim Lewis jim@synthworks.com -- -- -- Description: -- Alert handling and log filtering (verbosi...	mit	3484d99e983733940e62175a63eeabb6	0.518008	5.88453	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/dds/dds_funcsim.vhdl	3	314,526	-- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013 -- Date : Thu Mar 27 13:22:53 2014 -- Host : macbook running 64-bit Arc...	gpl-2.0	359de52c1a6e83d111991329cadd6a15	0.65036	2.989507	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ALU/ALU/logical_unit.vhd	1	1,673	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:37:34 03/28/2016 -- Design Name: -- Module Name: logical_unit - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Re...	gpl-3.0	fe258e3dd031d0a094e139c6ed8d40af	0.580395	3.456612	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/flt_log/flt_log_addsub_taylor_combiner_fabric.vhd	2	14,343	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	4f547f0317083daea1be6f5470da9c6a	0.934184	1.889972	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/axi_wrapper_output_fifo.vhd	2	14,518	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	402043c3ede0fc7a3b8a68ce5c629045	0.936424	1.875711	false	false	false	false
amerryfellow/dlx	alu/adder/p4adder.vhd	1	2,070	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use WORK.alu_types.all; -- Entity entity P4ADDER is generic( N: integer:= NSUMG ); port ( A: in std_logic_vector(N-1 downto 0); B: in std_logic_vector(N-1 downto 0); Cin: in std_logic; S: out std_logic_vec...	gpl-3.0	10b73aea1c83a2b877148d581d16b313	0.636232	2.709424	false	false	false	false
keith-epidev/VHDL-lib	top/lab_6/ip/clk_base/clk_base_funcsim.vhdl	1	7,903	-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014 -- Date : Tue May 13 22:55:34 2014 -- Host : macbook running 64-bit Arch Linux -- ...	gpl-2.0	ba543bc13e09a35ed5bd84f268cbd325	0.62723	3.297038	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/r22_bf_sp.vhd	2	87,575	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	d83aef884b0f34820adcc2c7eb4ac428	0.953446	1.820573	false	false	false	false
keith-epidev/VHDL-lib	top/lab_5/part_1/ip/fft/floating_point_v7_0/hdl/fix_to_flt_conv/fix_to_flt_conv_exp.vhd	2	19,122	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	0854d8ee35cdfc210d570b482707ea08	0.938396	1.863198	false	false	false	false
keith-epidev/VHDL-lib	top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/shared/shift_msb_first.vhd	3	21,177	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	gpl-2.0	1909c4b1c55291d10ba7c7d02521016c	0.939888	1.844365	false	false	false	false
FlatTargetInk/UMD_RISC-16G5	ProjectLab2/Shadow_Reg_No_VGA/Shadow_EX_NoVGA/ipcore_dir/EXTERNAL_MEMORY/simulation/EXTERNAL_MEMORY_synth.vhd	2	7,928	-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Synthesizable Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains c...	gpl-3.0	6e00492902c85d6b8ade706eb7eacfc2	0.567356	3.793301	false	false	false	false
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA	System Design Source FIle/ipshared/xilinx.com/xbip_dsp48_addsub_v3_0/dcc1fbbe/hdl/xbip_dsp48_addsub_v3_0.vhd	2	10,258	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect ke...	mit	6fba5454ba0c6cc4bc20cb649514e10c	0.926886	1.909531	false	false	false	false

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